This application note talks about the Introduction to phase-locked loop system modeling. The issue about linear PLL model is presented after introduction. The main topic of this application note is divided into 5 section : Introduction, A linear PLL model in the continuous-time domain (S-domain), Modeling of digital PLL (DPLL) in the discrete time domain (Z-domain), Stability and steady-state error study of the DPLL system, and A design example.

The section A linear PLL model in the continuous-time domain (S-domain) contains the explaination of A linear model of the PLL in S-domain, Phase detector, Loop filter, VCO—voltage-controlled oscillator. The detail about A linear model of PLL in discrete time domain, Mapping the poles of a second-order system from S-domain to Z-domain, and Implementation of a second-order DPLL are presented in section Modeling of digital PLL (DPLL) in the discretetime domain (Z-domain). section Stability and steady-state error study of the DPLL system describes about Stability of the DPLL system, Steady-state error analysis of the DPLL, Phase error analysis, and Frequency error analysis. The explaination about Design requirements is described in section A design example.

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