Reducing PCB Design Costs: From Schematic Capture to PCB Layout
By Rend at 19 March, 2010, 6:52 am
This application note talks about reducing PCB costs from schematic capture to PCB layout. The issues about how to reduce the cost of PCB designs is explained in detail in this note. This application note is divided into 5 section: The basics, Schematic libraries, PCB libraries, The netlist file, and Save time and avoid errors.
The section the basics tells about schematic capture packages, PCB layout packages, and design rules. The symbol libraries, schematic library, footprint attribute, user library and schematic capture tool are described in section schematic libraries. The section PCB libraries explains about PCB libraries, the footprints designated by industry standard, surface-mount through-hole devices, decal, pads, and electrical pin number. The explaination about netlist file, schematic databases, PCB databases, error in processing netlist file, rubber band information, and PCB routing are described in detail in section the netlist file. The save time and avoid errors section talks about how to avoid the erors, the back-annotation, and verification of the schematic and board files.
Download/View this Application Note.
No comments yet.